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[XiangShan Biweekly 110] 20260902

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 110th issue of the biweekly report.

Regarding the recent development progress of XiangShan, the frontend has fixed several branch-prediction and instruction-fetch issues and optimized uBTB training and IFU/ICache timing; the backend has advanced V3 register-file refactoring; the memory and cache subsystem has fixed several issues while continuing V3 development; XSAI has fixed matrix decoding, memory-access, and operand-wakeup issues and improved DiffTest and CI; in terms of infrastructure, FPGA DiffTest, NEMU/QEMU checkpointing, and GSIM build and simulation capabilities have been enhanced, while XS-GEM5 model calibration and performance exploration have continued.

Special thanks to community contributor muke101 for providing an open-source gem5 implementation of the PHAST memory-dependence prediction algorithm through a GitHub issue. XS-GEM5 further refactored and optimized this implementation.

We are also pleased to announce that the XiangShan team and Professor Trevor E. Carlson of the National University of Singapore will jointly host a workshop entitled Agile Development and Verification for Chips during MICRO 2026 in Greece. Scheduled for October 31, the workshop is now accepting submissions from the community. Please visit the submission website for details and to submit your work. We look forward to meeting you in Greece for an engaging exchange of ideas!

Recent Developments

Frontend

  • Bug fixes
  • Fix canonical-address checks for frontend PCs and add related simulation tests (#6340)
  • Add the notCfiTaken signal to the IFU redirect canTrain condition (#6398)
  • Flush pending write requests when resetting TAGE useful counters to prevent stale requests from overwriting the reset results (#6377)
  • Prevent TAGE from rereading the prediction table when using the base prediction (#6356)
  • Prevent a spurious s3_override when both BPU S1 and S3 predict not taken (#6417)
  • Update BTB replacement state on training accesses instead of prediction accesses (#6348)
  • Performance optimizations
  • Maintain UseAltOnNa based on predictor-table training state to reduce branch aliasing and register overhead (#6328)
  • Train the uBTB through both the resolve and fast-train paths to reduce extra bubbles after a misprediction redirect (#6237)
  • PPA optimizations
  • Precompute t0_firstMispredictMask to improve the timing of the FTQ-to-BPU train-cache write path (#6375)
  • Move the pre-decode and maybeRvc logic and register ICache data to improve the timing of the IFU/ICache instruction-alignment path (#6220)
  • Code refactoring
  • Move vtype generation from Decode to the IBuffer so each instruction carries its corresponding vtype and specvtype (#6376)
  • Use a PNR pointer to determine 2-prefetch and 2-fetch eligibility instead of a fixed distance from the BPU pointer (#6378)

Backend

  • Code refactoring
  • Use the lower bits of the physical-register index as the bank index in the banked register file to balance entries across banks and avoid compilation failures when the last bank is empty (#6357)
  • Move vtype generation from Decode to the IBuffer so each instruction carries its corresponding vtype and specvtype into the backend (#6376)

MemBlock and Cache

  • RTL features
  • Increase the configured openLLC capacity to 32 MB (#6401)
  • Implement and integrate a dedicated L3 stash prefetch path, including the L1-side bridge, CHI StashOnceShared requests, and openLLC stash-refill handling (XSCache #25, #6274)
  • Add performance counters for TLBs, request filters, page-table walkers, and L2TLB completion paths, and correct the PageCache hit conditions (#6383)
  • Add an F-POP L2 prefetch feedback controller that adjusts prefetchers using hit, latency, pollution, and contention feedback (XSCache #24)
  • Bug fixes
  • Align the CSR-change TLB flush latency between the frontend and MemBlock to prevent old-epoch PTW requests from crossing the flush boundary (#6421)
  • Fix the L3 prefetch receive-port generation condition and check normal MSHR TxnIDs against the stash-reserved space before encoding (XSCache #28)
  • Fix a deadlock in which a non-oldest cross-page unaligned store injects a tail request and continuously blocks the oldest request (#6382)
  • Complete the prefetch request-enable vector so request enables remain synchronized across six prefetchers (XSCache #27)
  • Allow secondary-miss merging only when the MissEntry request is valid (#6308)
  • (V2) Kill an unfinished hardware-prefetch request when VSegment takes over DCache load port 0 (#6389)
  • Timing Optimizations
  • Change DCache WritebackQueue release arbitration from round-robin to lowest-index-first (#6379)

XSAI

  • Bug fixes
  • Fix the MLCT transposed data layout and C MatrixReg read addresses for MSC/MSCT (XSAI #106, CUTE #38)
  • Fix misdecoding of msetcfg/mgetcfg (XSAI #107)
  • Fix state desynchronization between matrix memory-access AccessAckData responses and HintQueue (XSAI #110, XSAICache #6)
  • Fix missed wakeups for delayed Mx operand writebacks that could permanently block MLS instructions (XSAI #111)
  • Code quality
  • Remove unused matrix commit and scheduler feedback interfaces (XSAI #113)
  • Optimize CI: parallelize EMU and nightly regressions (XSAI #114, XSAI #116)
  • Debugging tools
  • Add AME mcfg state comparison to DiffTest (XSAI #107, difftest #944, NEMU #1172)
  • Support 16-byte store checker events (XSAI #112)
  • Handle MMA operand retrieval failures and improve AMU event diagnostics (difftest #926, difftest #927)

Infra

  • FPGA DiffTest
  • Support runtime configuration of CPU AXI channel delays (difftest #950)
  • Fix repeated handshakes in the DiffTest Squash data path (difftest #946)
  • Allow FPGA builds to filter verification signals with low debugging value and high area overhead (difftest #948)
  • Extend FPGA partition constraints for OpenLLC and update the Kunminghu flash initialization firmware (env-scripts #162)
  • Fix inter-FPGA and asynchronous-path timing constraints, and support runtime clock adjustment at a fixed CPU/RTC ratio (env-scripts #159, env-scripts #161)
  • NEMU Reference Model
  • Add nexus-am RVH bare-metal regression tests to CI (NEMU #1162)
  • Fix the final RVH TLB to restore the MBMC page-table level on hits (NEMU #1171)
  • Fix incomplete invalidation of HostTLB entries derived from superpages when Linux THP issues an address-specific SFENCE.VMA (NEMU #1175)
  • Sampling and Checkpointing
  • Enable Linux Transparent Huge Pages to improve performance for selected workloads (workload-builder #54)
  • Add UART16550 support to QEMU and align its serial address and parameters with the XiangShan platform (qemu #17)
  • Make the serial port address configurable in libcheckpoint (LibCheckpoint #27)
  • Improve the QEMU profilingv2 plugin by explicitly starting profiling via nemu_trap, speeding it up by 23% (qemu #16)
  • Optimize the NEMU SimPoint profiling hot path, speeding it up by about 20% (NEMU #1178)
  • GSIM Simulator
  • Add a --threads option to control the FIRRTL parser worker count and cap it according to the CPUs available to the process (gsim #119)
  • Improve CI and release workflows with Dependabot, unified dependency installation, multiple LLVM versions, and ARM64 builds (gsim #121)
  • Optimize code generation for one-dimensional array assignments by using memcpy instead of element-wise copies when applicable, significantly reducing generated-code compilation time (gsim #125)

XS-GEM5

Performance Evaluation

Processor and SoC parameters are as follows:

Parameters Options
Commit 53a957667
Date 2026/08/21
L1 ICache 64KB
L1 DCache 64KB
L2 Cache 2MB
L3 Cache 16MB
LSU 3ld2st
Bus protocol CHI
Memory configuration DDR4-3200

The SPEC CPU2006 scores are as follows:

SPECint 2006 @ 3GHz GCC16 XSCC SPECfp 2006 @ 3GHz GCC16 XSCC
400.perlbench 55.02 53.33 410.bwaves 123.07 105.77
401.bzip2 29.89 30.60 416.gamess 58.70 55.81
403.gcc 58.27 41.61 433.milc 71.84 68.77
429.mcf 72.01 62.81 434.zeusmp 77.33 67.78
445.gobmk 43.70 42.34 435.gromacs 40.04 35.10
456.hmmer 54.59 67.12 436.cactusADM 85.01 93.51
458.sjeng 41.66 41.74 437.leslie3d 61.20 61.31
462.libquantum 138.17 305.05 444.namd 44.25 45.26
464.h264ref 69.92 75.51 447.dealII 64.71 79.14
471.omnetpp 48.18 47.76 450.soplex 59.78 72.28
473.astar 33.06 32.50 453.povray 78.25 73.65
483.xalancbmk 85.35 92.62 454.Calculix 41.80 40.77
GEOMEAN 55.75 58.70 459.GemsFDTD 74.41 73.41
465.tonto 55.70 37.80
470.lbm 127.10 146.69
481.wrf 58.65 44.97
482.sphinx3 61.39 64.02
GEOMEAN 66.14 63.98

Compilation parameters are as follows:

Parameters GCC16 XSCC
Compiler gcc16 xscc
Optimization level O3 O3
Memory library jemalloc jemalloc
ISA configuration RVA23-based (vector disabled) RV64GCB
-ffp-contraction fast fast
Linker optimization -flto -flto
Floating-point optimization -ffast-math -ffast-math
-mcpu - xiangshan-kunminghu

Note: We use SimPoint to sample the programs and create checkpoint images based on our custom checkpoint format, with a SimPoint clustering coverage of 100%. The above scores are estimates based on program segments, not full SPEC CPU2006 evaluations, and may differ from actual chip performance.

Editors: Yanjun Li, Jinhong Zeng, Zechen Yang, Hanle Zhang, Kunlin You, Hao Zhen, Yiming Yan