Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 98th issue of the biweekly report.
Kunminghu V2 has been returned from the fab! We are currently conducting intensive testing, and more information will be disclosed in the future. Stay tuned!
Regarding the recent development progress of XiangShan, the frontend has fixed some performance bugs in BPU, the backend has optimized the timing of some modules, and the memory subsystem continues to undergo refactoring and testing.
Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 97th issue of the biweekly report.
Regarding the recent development progress of XiangShan, ~~the XiangShan team had a happy Chinese New Year holiday~~. For more details, please refer to the Recent Developments section. ~~But it's not all for nothing~~, we also prepared a little fun fact about the development of XiangShan for everyone.
Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 96th issue of the biweekly report.
Happy Chinese New Year! Welcome to our biweekly column during the Spring Festival, and we wish you in the new year:
Frontend has the precise prediction like a unicorn, and career opportunities are never misjudged;
The pipeline runs like a thousand horses, everything goes smoothly and in parallel;
The memory subsystem is as vigorous as a dragon horse, and the happy data is inexhaustible;
The memory access path is like a vast grassland, and the happy address is always mapped in the heart;
The cache hierarchy is as warm as spring, and every precious memory is within reach;
The bus bandwidth is like a thousand-mile horse, and the good luck signal arrives immediately at your side!
We also shared the wonderful review of the tutorial hosted by XiangShan team at HPCA 2026. Please visit https://tutorial.xiangshan.cc/hpca26/ to review the content of this tutorial and get the slides. The next tutorial will be held at ISCA 2026 in Raleigh, North Carolina, USA in late June, and we look forward to seeing you again!
Regarding the recent development progress of XiangShan, ~~the XiangShan team is also having a happy Chinese New Year.~~ For the limited details, please see the recent progress section.
Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 95th issue of the biweekly report.
The high-performance DDR4 memory controller IP, Baiyang, developed by the XiangShan team has been officially released! If you haven't read it yet, please check out our Baiyang release article for more details. Here, we would like to share an exclusive story with you. On January 31st, XiangShan presented a tutorial at HPCA 2026, which included an introduction to Baiyang. The night before the presentation, Baiyang was still being prepared for open source, and the repository was made public just before the tutorial started the next day. ~~Deadlines are indeed the best productivity boosters~~.
Last week, we introduced new GCC15 and XSCC compilers. These two compilers offer more than 10% performance improvement compared to the existing GCC12. Now, XiangShan's SPEC CPU2006 performance has reached 18.5 points/GHz. In this issue of the biweekly report, we provide a comparative analysis of different compilers. In future development, we will gradually switch to GCC15 and XSCC compilers, while focusing more on compiler and hardware co-optimization. The specific scores for different compilers are still in the performance evaluation section, so stay tuned!
In terms of recent development progress, on the frontend side, MBTB has introduced the LRU replacement algorithm and uses accurate prediction results from TAGE-SC for updates to improve branch prediction accuracy. On the backend side, an I2F functional unit has been added to support i2f type instructions of FMV and FCVT, and og1Payload has been added to the integer IQ to optimize selection timing. In terms of memory access and cache, the timeout judgment logic in Sbuffer has been fixed, and the timeout threshold is configured through SMBLOCKCTL in CSR. For more details, please refer to the recent progress section.
Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 94th issue of the biweekly report.
In terms of XiangShan development, the frontend team is wrapping up the 1-taken 1-fetch architecture while exploring the 2-taken 2-fetch architecture; the backend team continues to advance the design of the vector unit and refactor multiple modules; the memory access team has fixed several bugs and is continuing to explore prefetching and MDP.