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[XiangShan Biweekly 108] 20260803

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 108th issue of the biweekly report.

On July 21, renowned computer expert Mao Decao visited BOSC and gave a lecture titled "Artificial Intelligence and Processor Chips."

Mao Decao's lecture

Mao's connection with XiangShan goes beyond this visit. He also wrote RISC-V CPU Chip Design: XiangShan Source Code Annotated. He began writing the book in 2021 at the age of 76, working alone for nearly 10 hours a day at times. It took him 3.5 years to complete, by which time he was 79 years old.

The core XiangShan team also had an in-depth discussion with Mao, listening to the valuable experience and profound insights into the industry that he has accumulated over the years. We are deeply honored that Mao agrees with XiangShan's design philosophy. We will continue striving to improve XiangShan and make it a benchmark in the open-source processor field.

Regarding the recent development progress of XiangShan, the frontend continues to optimize timing; the backend fixes some bugs in V2 and calibrates the topdown counter; the memory and cache implement a dual-channel TileLink bus and optimize the LSU; XSAI updates the AME version and fixes several bugs.

【香山双周报 108】20260803 期

欢迎来到香山双周报专栏,我们将通过这一专栏定期介绍香山的开发进展。本次是第 108 期双周报。

7 月 21 日,著名计算机专家毛德操老师到访开芯院,并为大家带来了题为《人工智能与处理器芯片》的讲座。

毛德操老师讲座

毛老师与香山的缘分不止于此,他还撰写过《RISC-V CPU 芯片设计:香山源代码剖析》。这本书是毛老师在76岁(2021年),自己 1 个人,时常工作近 10 小时/天,花费 3.5 年的时间著作而成。成书时,毛老师已经79岁。

香山的核心团队也与毛老师进行了深入交流,听取毛老师多年来对产业界的深刻见解和宝贵经验。毛老师能够认同香山的设计理念,这让我们感到非常荣幸,我们也将继续努力,将香山越做越好,成为开源处理器领域的标杆。

关于香山近期开发进展,前端继续优化时序;后端修复了 V2 的一些 bug,同时校准了 topdown 计数器;访存与缓存实现了双通道 TileLink 总线,并对 LSU 进行了优化;XSAI 更新了 AME 版本,同时修复了若干 bug。

[XiangShan Biweekly 107] 20260720

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 107th issue of the biweekly report.

Regarding the recent development progress of XiangShan, the frontend has fixed timing issues in multiple modules and resolved some bugs reported by the community; the backend has fixed several bugs related to CSR, debug mode, and performance events, and synchronized V2 fixes to V3; in terms of memory access and caching, support for pre-allocated StoreQueue, LoadQueueReplay fast wakeup, and dual-port L1-L2 TileLink bus has been added, along with multiple bug fixes; XSAI has fixed control signals for load/store whole C instructions and added support for configurable multi-channel memory access in CUTE.

【香山双周报 107】20260720 期

欢迎来到香山双周报专栏,我们将通过这一专栏定期介绍香山的开发进展。本次是第 107 期双周报。

关于香山近期开发进展,前端修复了多个模块的时序问题,并修复了一些由社区发现的 bug;后端修复了多个 CSR、调试模式和性能事件相关的 bug,并同步了 V2 的修复到 V3;访存与缓存方面,支持了预分配 StoreQueue、LoadQueueReplay 快速唤醒和双端口 L1-L2 TileLink 总线,并修复了多个 bug;XSAI 修复了 load/store whole C 指令的控制信号,并支持可配置的 CUTE 多通道访存。

[XiangShan Biweekly 106] 20260706

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 106th issue of the biweekly report.

The XiangShan tutorial at ISCA 2026 was held ~~not so~~ smoothly! Although some students could not present on site due to visa issues, we quickly arranged backup speakers and ultimately ensured that the tutorial was completed with high quality. Special thanks to everyone who follows XiangShan's development!

Regarding the recent development progress of XiangShan, the frontend added support for the 2-fetch feature; the memory subsystem optimized DCache, Sbuffer, and the prefetchers; XSAI supported new matrix memory access modes and updated the instruction extension.

【香山双周报 106】20260706 期

欢迎来到香山双周报专栏,我们将通过这一专栏定期介绍香山的开发进展。本次是第 106 期双周报。

ISCA 2026 香山 tutorial ~~不那么~~顺利举办!虽然一些同学因为签证原因没能现场报告,但我们紧急召集了替补,最终保证了 tutorial 高质量完成。特别感谢每一位关注香山发展的伙伴们!

关于香山近期开发进展,前端支持了 2-fetch 特性;访存优化了 DCache、Sbuffer 和预取器;XSAI 支持了新的矩阵访存模式,同时更新了指令扩展。

[XiangShan Biweekly 105] 20260623

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 105th issue of the biweekly report.

The RISC-V Summit Europe has successfully concluded! Professor Bao Yungang, Deputy Director of the Institute of Computing Technology, Chinese Academy of Sciences, and Chief Scientist of the Beijing Open Source Chip Research Institute, shared his experience at the summit and provided insights into the future prospects of RISC-V development. We welcome everyone to engage in discussions with us!

Regarding the recent development progress of XiangShan, the frontend continues to optimize timing; the backend and memory access have fixed some functional bugs while optimizing DCache and Sbuffer performance; XSAI has supported the BF16 extension, and HBL2 has implemented PutFullData for TL-TL and TL-CHI.

【香山双周报 105】20260623 期

欢迎来到香山双周报专栏,我们将通过这一专栏定期介绍香山的开发进展。本次是第 105 期双周报。

RISC-V 欧洲峰会圆满落幕!中国科学院计算技术研究所副所长、北京开源芯片研究院首席科学家包云岗研究员与大家分享了他的参会感受,以及对 RISC-V 发展前景的展望,欢迎大家与我们交流讨论!

关于香山近期开发进展,前端继续优化时序;后端和访存修复了一些功能 bug,同时优化了 DCache 与 Sbuffer 性能;XSAI 支持了 BF16 扩展,HBL2 实现了 TL-TL 与 TL-CHI 的 PutFullData。

[XiangShan Biweekly 104] 20260608

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 104th issue of the biweekly report.

We are very excited to share with you an important component in the "XiangShan" + "Ruyi" ecosystem: RuyiSDK! This is a one-stop development resource management platform for RISC-V architecture, which integrates toolchains, simulators, runtime environments, and debugging tools based on the ruyi package manager and IDE plugin system, providing full-process development support. The platform has built a comprehensive matrix of RISC-V development boards and operating system support, providing developers with a more convenient operating experience and serving as an important infrastructure for promoting RISC-V development and ecosystem construction.

You can get more information through the following links:

RISC-V European Summit is ongoing! The XiangShan team has multiple talks and posters at the summit, and the detailed schedule can be found here.

In the opening report of the RISC-V International, CEO Andrea Gallo introduced the application of XiangShan in high-performance server scenarios.

Andrea Gallo introducing the application of XiangShan in high-performance server scenarios

Deputy Director of the Institute of Computing Technology, Chinese Academy of Sciences, and Chief Scientist of Beijing Open Source Chip Research Institute, Researcher Bao Yungang gave a report titled "XiangShan Practice: The Path to Industrial Deployment of Open-Source High-Performance RISC-V Processor", introducing the industrial deployment path of XiangShan.

Researcher Bao Yungang introducing the industrial deployment path of XiangShan

XiangShan family

We also held the workshop of Unity Chip for the first time, sharing with everyone the exploration and practice of software-native open-source chip intelligent crowdsourcing verification.

Unity Chip workshop

Regarding the recent development progress of XiangShan, the frontend continues to optimize timing while reducing redirect latency; the backend implements some new features and instruction set extensions; the memory subsystem fixes some bugs while optimizing L2 timing; XSAI optimizes code structure while advancing HBL2 support for CHI.

【香山双周报 104】20260608 期

欢迎来到香山双周报专栏,我们将通过这一专栏定期介绍香山的开发进展。本次是第 104 期双周报。

我们非常高兴地与大家分享“香山”+“如意”生态中的重要组成部分 RuyiSDK!这是一个面向 RISC-V 架构的一站式开发资源管理平台,依托 ruyi 包管理器与 IDE 插件体系,整合工具链、模拟器、运行时环境及调试工具,提供全流程开发支持。平台构建了完善的 RISC-V 开发板与操作系统支持矩阵,为开发者提供更便捷的操作体验,是推动 RISC-V 开发与生态建设的重要基础设施。

大家可以通过以下链接获取更多信息:

RISC-V 欧洲峰会正在举行!香山团队在峰会上有多个 talk 和 poster,详细日程见这里。

在 RISC-V 国际协会的开场报告中,CEO Andrea Gallo 介绍了香山在高性能服务器场景的应用。

Andrea Gallo 介绍香山在高性能服务器场景的应用

中国科学院计算技术研究所副所长、北京开源芯片研究院首席科学家包云岗研究员作了题为 XiangShan Practice: The Path to Industrial Deployment of Open-Source High-Performance RISC-V Processor 的报告,介绍了香山的产业部署之路。

包云岗研究员介绍香山的产业部署之路

香山家族

我们还首次举办了万众一芯的 workshop,与大家分享软件原生的开源芯片智能众包验证探索与实践。

万众一芯 workshop

关于香山近期开发进展,前端继续优化时序,同时降低了重定向延迟;后端实现了一些新特性与指令集扩展;访存修复了一些 bug,同时优化了 L2 的时序;XSAI 优化了代码结构,同时推进了 HBL2 对 CHI 的支持。