Exception and Interrupt
Overview
Exceptions and interrupts are mechanisms by which the processor jumps from the normal program execution flow to privileged mode. They are used to handle various unexpected or anticipated events. These mechanisms help the processor address issues encountered during execution, maintain system stability, and respond to external events.
-
An exception refers to a situation where the processor encounters an issue while executing the current instruction that prevents further execution, requiring an immediate halt to the normal program flow and entry into an exception handler. Exceptions are typically synchronous, meaning they are directly related to the currently executing instruction. Common types of exceptions include:
-
Illegal instruction: When the processor encounters an unrecognizable or unexecutable instruction, it generates an illegal instruction exception.
- Address misaligned exception: When performing load or store operations, if the accessed memory address is misaligned, the processor will raise an exception.
- Page fault: In a virtual memory system, a page fault exception occurs when a page table entry is missing or memory access permissions are insufficient.
- Environment call (system call): When an application requests kernel services through a specific instruction, it also triggers an exception.
- Hardware Error: When the processor executes a load or store operation and the bus address request corresponds to data that does not exist, the processor triggers an exception.
- Double Trap: When the processor is executing an exception/interrupt handler and another exception/interrupt occurs, the processor triggers an exception to handle the double trap.
-
An interrupt is a signal triggered by external hardware devices (such as timers, peripherals, etc.), requesting the processor to pause the currently executing program and handle these external events. Interrupts are asynchronous, meaning they are unrelated to the current instruction execution and can occur at any time. Based on their sources, interrupts can be categorized into the following types:
-
Hardware interrupts: Generated by external hardware devices, such as I/O requests from peripherals, timer interrupts, etc.
- Software interrupts: Triggered by software for interacting with the operating system or performing certain system-level tasks.
- A trap is a mechanism where the processor switches from user mode or a lower privilege level to a privileged mode (such as kernel mode) to handle events. The processor captures exceptions or interrupts through the trap mechanism, saves context information, and jumps to the corresponding handler. After processing is complete, the processor restores the previous execution state via return instructions (such as mret or sret) and continues executing the original program.
Exception
Kunminghu V2R2 supports various exceptions, as shown in the following table:
| Exception number | Trap cause | tval update value | tval2 update value |
|---|---|---|---|
| 0 | Instruction address misaligned | 0 | 0 |
| 1 | Instruction fetch permission exception (non-page-crossing) | Instruction Start Address | 0 |
| 1 | Instruction fetch permission fault (cross-page) | Next Page Start Address | 0 |
| 2 | Illegal instruction | Illegal instruction encoding | 0 |
| 3 | Breakpoint | Exception instruction address | 0 |
| 3 | EBREAK instruction | 0 | 0 |
| 4 | LOAD address misaligned | Memory Access Start Address | 0 |
| 5 | LOAD Permission Exception | Actual fault starting address | 0 |
| 6 | STORE/AMO Address Misaligned | Memory Access Start Address | 0 |
| 7 | STORE/AMO permission exception | Actual fault starting address | 0 |
| 8 | U-ECALL | 0 | 0 |
| 9 | S-ECALL | 0 | 0 |
| 10 | VS-ECALL | 0 | 0 |
| 11 | M-ECALL | 0 | 0 |
| 12 | Instruction Page Fault (Non-page-crossing) | Instruction Start Address | 0 |
| 12 | Instruction page fault (page-crossing) | Next Page Start Address | 0 |
| 13 | LOAD page fault (non-cross-page) | Memory Access Start Address | 0 |
| 13 | LOAD page fault (page-crossing) | Actual fault starting address | 0 |
| 15 | STORE/AMO Page Fault (Non-page-crossing) | Memory Access Start Address | 0 |
| 15 | STORE/AMO page fault (cross-page) | Actual fault starting address | 0 |
| 16 | Double Trap Exception | 0 | Trap cause code of the second exception. |
| 19 | Hardware error | Actual fault starting address | 0 |
| 20 | Guest instruction page fault (non-page-crossing) | Instruction Start Address | Corresponding GPA |
| 20 | Guest instruction page fault (cross-page) | Next Page Start Address | Actual fault GPA |
| 21 | Guest LOAD page fault (non-cross-page) | Memory Access Start Address | Corresponding GPA |
| 21 | Guest LOAD page fault (cross-page) | Actual fault starting address | Actual fault GPA |
| 22 | Virtualization instruction exception | Illegal instruction encoding | 0 |
| 23 | Guest STORE/AMO page fault (non-page-crossing) | Memory Access Start Address | Corresponding GPA |
| 23 | Guest STORE/AMO Page Fault (Cross-page) | Actual fault starting address | Actual fault GPA |
Note: Xiangshan does not actually have instruction address misalignment exceptions.
We take machine mode as an example to introduce the steps of exception handling.
Exception Response
Step 1: The processor saves the PC where the exception occurred into mepc.
Step 2: Set the interrupt flag bit of mcause to 0, write the exception number into mcause, and modify the corresponding mtval.
Step 3: Save the MIE bit of mstatus to the MPIE bit, then clear the MIE bit. Set the MPV bit and MPP bit of mstatus to the current Virtual Mode and Privilege Mode respectively, and modify the corresponding GVA bit as needed.
Step 4: Fetch and execute the corresponding instruction based on mtvec.
Exception return
Exception return is implemented via the mret instruction, which performs the following operations.
- Restore PC based on mepc.
- Restore the MIE bit of mstatus according to the MPIE bit of mstatus.
- Change the current Privilege Mode to the MPP bit of mstatus, and if the MPP bit is machine mode, set the Virtual Mode to 0; otherwise, set it to the MPV bit of mstatus.
Interrupts.
Kunminghu V2R2 supports various interrupts, as shown in the following table:
| Interrupt number | Trap cause |
|---|---|
| 1 | Supervisor Software Interrupt (SSI) |
| 2 | Virtual Supervisor Software Interrupt (VSSI) |
| 3 | Machine-mode Software Interrupt (MSI) |
| 5 | Supervisor mode timer interrupt (STI) |
| 6 | Virtual Supervisor Timer Interrupt (VSTI) |
| 7 | Machine mode timer interrupt (MTI) |
| 9 | Supervisor mode external interrupt (SEI) |
| 10 | Virtual Supervisor External Interrupt (VSEI) |
| 11 | Machine-mode external interrupt (MEI) |
| 12 | Supervisor Guest External Interrupt (SGEI) |
| 13 | Local Counter Overflow Interrupt (LCOFIP) |
| 16-23 | Standard Local Interrupt |
| 24-31 | Custom Interrupt |
| 32-47 | Standard Local Interrupt |
| 48-63 | Custom Interrupt |
We use machine mode as an example to explain the steps of interrupt handling
Interrupt Priority
The interrupt priorities of Kunminghu V2R2 are as shown in the following table:
| Interrupt Priority | Group | Number | Descrption |
|---|---|---|---|
| Highest | Custom Group 0 | 63, 31, 62 | Highest Priority Custom Interrupt |
| 61, 30, 60 | |||
| Local Group 0 | 47, 23, 46 | High-priority Local interrupt | |
| 45, 22, 44 | |||
| 43, 21, 42 | |||
| 41, 20, 40 | |||
| Custom Group 1 | 59, 29, 58 | Second highest priority Custom interrupt | |
| 57, 28, 56 | |||
| TSEO Group | 11, 3, 7 | Machine Mode Interrupts: External, Software, Timer | |
| 9, 1, 5 | Supervisor Mode Interrupts: External, Software, Timer | ||
| 12 | Supervisor Guest External Interrupt | ||
| 10, 2, 6 | Virtual Supervisor Mode Interrupts: External, Software, Timer | ||
| 13 | Local counter overflow interrupt | ||
| Custom Group 2 | 55, 27, 54 | Medium Priority Custom Interrupt | |
| 53, 26, 52 | |||
| Local Group 1 | 39, 19, 38 | Low-priority Local interrupt | |
| 37, 18, 36 | |||
| 35, 17, 34 | |||
| 33, 16, 32 | |||
| Custom Group 3 | 51, 25, 50 | Lowest priority Custom interrupt | |
| Lowest | 49, 24, 48 |
Interrupt Response
Step 1: After executing the current instruction, the processor stores the PC of the next instruction into mepc.
Step 2: Set the interrupt flag bit of mcause to 1, write the exception number into mcause, and set mtval to 0.
Step 3: Save the MIE bit of mstatus to the MPIE bit, then clear the MIE bit. Set the MPV bit and MPP bit of mstatus to the current Virtual Mode and Privilege Mode respectively, and modify the corresponding GVA bit as needed.
Step 4: Fetch and execute the corresponding instruction based on mtvec.
Interrupt return
- Restore PC based on mepc.
- Restore the MIE bit of mstatus according to the MPIE bit of mstatus.
- Change the current Privilege Mode to the MPP bit of mstatus, and if the MPP bit is machine mode, set the Virtual Mode to 0; otherwise, set it to the MPV bit of mstatus.