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Backend overview

The Backend is the back-end of the Xiangshan processor, which includes multiple components such as instruction decode (Decode), rename (Rename), dispatch (Dispatch), schedule (Schedule), issue (Issue), execute (Execute), writeback (Writeback), and retire (Retire), as shown in 此图.

Overall Backend Architecture

Basic technical specifications

  • 6-wide decode, rename, and dispatch
  • 224-entry integer register file, 192-entry floating-point register file, 128-entry vector register file
  • Move instruction elimination
  • Instruction fusion
  • 160-entry ROB
  • Supports ROB compression (up to 6 uops per entry)
  • Up to 8 entries retired per cycle
  • Snapshot recovery
  • Rename Buffer
  • 256-entry RAB
  • Instruction commit and register writeback
  • Integer, floating-point, and vector computation