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XiangShan Design Document
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Frontend
Frontend
Branch Prediction Unit
Branch Prediction Unit
FallThrough
Micro Btb (ubtb)
Ahead Btb (abtb)
Micro Tage (utage)
Main Btb (mbtb)
TAgged GEometic History Length predictor (tage)
Statistical Corrector (sc)
Indirect Target Tage (ittage)
Return Address Stack (ras)
History Register
History Register
Table of contents
Path History Register (PHR)
Common History Register (CommonHR)
Saturate Counter
Fetch Target Queue
Fetch Target Queue
Instruction Fetch Unit
Instruction Fetch Unit
Pre-Decoder
Instruction Cache
Instruction Cache
MainPipe
PrefetchPipe
WayLookup
Array
MissUnit
Replacer
CtrlUnit
PC Class
PC Class
Backend
Backend
Control Block (CtrlBlock)
Control Block (CtrlBlock)
Decode
Rename
Dispatch
Reorder Buffer
Data Path (DataPath)
Data Path (DataPath)
DataPath
Og2ForVector
WbDataPath
WbFuBusyTable
BypassNetwork
Scheduling and Issue
Scheduling and Issue
Scheduler
IssueQueue
IssueQueueEntries
Execution
Execution
ExuBlock
ExuUnit
Function Unit (FunctionUnit)
Function Unit (FunctionUnit)
Integer Function Unit
Floating-Point Function Unit
Vector Function Unit
Memory Function Unit
Vector Floating-Point Unit (VFPU)
Control and Status Registers (CSR)
Hardware Performance Monitor (HPM)
Debug Module
Memory System
Memory System
Load-Store Unit (LSU)
Load-Store Unit (LSU)
Load Unit (LoadUnit)
Store Address Unit (StoreUnit)
Store Data Unit (StdExeUnit)
Atomic Operation Unit (AtomicsUnit)
Vector Memory Access
Vector Memory Access
Vector Load Split Unit (VLSplit)
Vector Store Split Unit (VSSplit)
Vector Load Merge Buffer (VLMergeBuffer)
Vector Store Merge Buffer (VSMergeBuffer)
Vector Segment Unit (VSegmentUnit)
Vector FOF Unit (VfofBuffer)
Load-Store Queue (LSQ)
Load-Store Queue (LSQ)
Load Queue (VirtualLoadQueu)
Read-After-Read Check (LoadQueueRAR)
Read-After-Write Check (LoadQueueRAW)
Load Replay Queue (LoadQueueReplay)
Uncache Load Unit (LoadQueueUncach)
Load Exception Buffer (LqExceptionBuffer)
Store Queue (StoreQueue)
Uncache Handling Unit (Uncache)
Store Commit Buffer (SBuffer)
Load Misaligned Access Unit (LoadMisalignBuffer)
Store Misaligned Access Unit (StoreMisalignBuffer)
Data Cache
Data Cache
Load Pipeline (LoadPipe)
Miss Queue (MissQueue)
Probe Queue (ProbeQueue)
Main Pipeline (MainPipe)
Writeback Queue (WritebackQueue)
Error Handling and Custom Fault Injection
Memory Management Unit (MMU)
Memory Management Unit (MMU)
L1TLB
Repeater
L2TLB
L2TLB
Page Cache
Page Table Walker
Last Level Page Table Walker
Hypervisor Page Table Walker
Miss Queue
Prefetcher
PMP & PMA
Cache Subsystem
Cache Subsystem
L2 Cache
L2 Cache
L2 Cache (CoupledL2)
Channel A Request Buffer (RequestBuffer)
Request Arbiter and Main Pipeline
Directory (Directory)
Data SRAM (DataStorage)
MSHR
Upstream TileLink Channels
Upstream TileLink Channels
SinkA
SinkC
GrantBuffer
Downstream CHI Channels
Downstream CHI Channels
TXREQ
RXRSP
RXDAT
RXSNP
TXDAT
TXRSP
P-Credit Management
Link Layer Controller (LinkMonitor)
MMIO Bridge (MMIOBridge)
Error Handling
Table of contents
Path History Register (PHR)
Common History Register (CommonHR)
History Register
Path History Register (PHR)
Common History Register (CommonHR)
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