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[XiangShan Biweekly 93] 20260105

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 93rd issue of the biweekly report.

This is the first issue of the biweekly report in 2026! In the past year of 2025, the XiangShan team has made solid progress and achieved multiple important milestones with high quality:

  • First industrial application. The second-generation XiangShan Nanhu has been integrated as the main control CPU into the latest generation chips by Moore Threads and Chipown Technology, with Moore Threads shipping tens of thousands of units; the third-generation XiangShan Kunminghu has completed product-level delivery for the first batch of SoC chips, with two companies completing SoC chip tape-out in October and November respectively, and will receive in Q1 2026.
  • Won the first Open Source Contribution Award from the CCF Architecture Committee of the China Computer Federation
  • The "XiangShan" open-source processor core was selected as one of the representative scientific research achievements of the Chinese Academy of Sciences in 2025 and was included in the New Year message of CAS President Hou Jianguo
  • Presented tutorials at top conferences such as ISCA, HPCA, MICRO, introducing the latest progress of XiangShan to the world
  • Multiple tools have been developed and papers published at top international conferences, such as GSIM (DAC25), DiffTest-H (MICRO25), TraceRTL (HPCA26), UCAgent, etc.
  • Several papers based on XiangShan evaluations have been published in top international conferences
  • Verification work has been continuously improved, successfully passing multiple milestone tests such as 8-core consistency verification and booting GUI OpenEuler
  • Kunminghu V3 became the new default branch, with the latest performance surpassing Kunminghu V2
  • Hosted community events such as RISC-V Hackathon and Documentation Bug Hunt, and had enthusiastic exchanges with friends around the world who care about the progress of XiangShan at the second XiangShan Open Source Community Conference
  • XiangShan Compiler (XSCC) released, XiangShan now has its own compiler
  • The AI intelligent agent UCAgent from the "One Chip for All" team was released, successfully hosting the first open-source chip hackathon

A new year means a new beginning. In 2026, XiangShan will continue to implement the new concept of "open source", continuously promote the iterative development of Kunminghu V3 and the construction of the open source community. We sincerely thank everyone for their companionship and support for XiangShan!

In terms of XiangShan development, the new front-end of 1-taken and 1-fetch has been basically completed; the back-end continues to advance the design and implementation of the new vector unit while refactoring existing code; the memory system continues to refactor modules such as MMU, LoadUnit, StoreQueue, L2, and fixes some bugs.

Recent Developments

Frontend

  • RTL feature
  • Implement MBTB replacer to only touch branches with taken prediction, allowing useless branches to be replaced from MBTB first (#5414)
  • Implement banked ITTAGE SRAM to reduce read-write conflicts (#5430)
  • Implement TAGE to store provider information into metaQueue to reduce reads during updates, thereby reducing read-write conflicts (#5400)
  • Bug Fix
  • Fix issue of incorrect read-write conflict conditions in ITTAGE SRAM (#5392)
  • Fix issue of other predictors being trained repeatedly when TAGE training is blocked (#5399)
  • Timing/Area optimization
  • Fix timing issues of WriteBuffer write ports in MBTB and TAGE (#5418, #5433)
  • Fix timing issues caused by large bit-width and poor selection of ABTB SRAM (#5417)
  • Code quality improvements
  • Rewrite parts of the Frontend top-level module that do not conform to the style guide and fix IDE warnings (#5395)
  • Rewrite index selection logic of ABTB and UBTB using AddrField class (#5397)
  • Clean up unused code in ABTB (#5456)
  • Debugging tools
  • Add MicroTAGE Trace (#5388)
  • Add ICache Trace (#5452)
  • Add numerous performance counters (#5442, #5443, #5289)

Backend

  • RTL new features
  • implementating the new design of V3 vector unit
  • Bug fixes
  • Fix backend TopDown interface connection issues (#5340)
  • Modify the value of mvendorid (#5367)
  • Fix Dispatch pipeline stall cycle counting issue (#5398)
  • Code optimizations
  • Make the connection of srcLoadDependencyUpdate more readable ([#5404](https://
  • Others

  • Update the list of backend code owners (#5342)

  • RTL new features

  • Advancing the new design implementation of the V3 vector unit
  • (V3) Modify the value of mvendorid (#5427)
  • (V3) Refactor the vimac64b module, implement the vimac gold model, and add corresponding interfaces to VecSimTop (YunSuan #193)
  • Bug fixes
  • (V3) Fix RAS action issue during commit (#5421)
  • (V2/V3) Fix priority issue causing illegal instruction exception when reading vl/vlenb in CSR read instructions (#5420, #5422)
  • (V3) Use basicDebugEn signal in diffVl debug interface (#5465)
  • (V2) Upgrade NEMU config to fix vfredusum issue (#5434)
  • Timing
  • (V3) Reduce one-cycle delay in redirect (#5378)
  • (V3) Move the selection of oldestExuRedirect from ctrlblock to intRegion (#5462)
  • (V3) Separate targetPc into trap and xret paths to optimize timing, handling exceptions and CSR FunctionUnit writebacks respectively (#5475)
  • Code optimizations
  • (V3) Remove some dead code (#5405, #5324)
  • (V3) Remove some code connecting with 0.U width (#5413)
  • (V3) Switch to using CSRs.scala file to keep track of CSR addresses (#5440)
  • (V3) Configure vl src separately in each parameter class in backend for easier maintenance (#5368)
  • Others

MemBlock and Cache

  • RTL new features
  • The refactoring and testing of MMU, LoadUnit, StoreQueue, L2, etc. is ongoing
  • Bug fix
  • Modify the pipe parameter of Pipeline to true in PerfetcgWrapper (#5275)
  • Fix the error of multi-writeback when storeMisalignBuffer is full (#5415)
  • Remove redundant BEU range exclusion in L2 (CoupledL2 #457)
  • Sync the pr in V2 to V3
  • Code refactoring
  • Remove fdpMonitor and fix some statistics bugs (#5272)
  • Debugging tools
  • Continuous improvement of CHI infrastructure CHIron
  • Develop a verification tool CHI Test for the new version of L2 Cache. Continuous progressing

Performance Evaluation

SPECint 2006 est. @ 3GHz SPECfp 2006 est. @ 3GHz
400.perlbench 38.38 410.bwaves 73.28
401.bzip2 27.53 416.gamess 55.10
403.gcc 48.17 433.milc 46.08
429.mcf 60.25 434.zeusmp 60.34
445.gobmk 37.30 435.gromacs 38.58
456.hmmer 44.20 436.cactusADM 54.30
458.sjeng 34.49 437.leslie3d 53.87
462.libquantum 127.76 444.namd 38.02
464.h264ref 63.36 447.dealII 62.95
471.omnetpp 43.19 450.soplex 54.69
473.astar 30.68 453.povray 61.24
483.xalancbmk 81.47 454.Calculix 19.40
GEOMEAN 48.07 459.GemsFDTD 44.60
465.tonto 36.34
470.lbm 104.91
481.wrf 48.88
482.sphinx3 56.16
GEOMEAN 50.55

Compilation parameters are as follows:

Parameters Options
Compiler gcc12
Optimization level O3
Memory library jemalloc
-march RV64GCB
-ffp-contraction fast

Processor and SoC parameters are as follows:

Parameters Options
Commit 64e7bff7f
Date 12/19/2025
L1 ICache 64KB
L1 DCache 64KB
L2 Cache 1MB
L3 Cache 16MB
LSU 3ld2st
Bus protocol TileLink
Memory latency DDR4-3200

Note: We use SimPoint to sample the programs and create checkpoint images based on our custom checkpoint format, with a SimPoint clustering coverage of 100%. The above scores are estimates based on program segments, not full SPEC CPU2006 evaluations, and may differ from actual chip performance.

Editors: Zhihao Xu, Junxiong Ji, Zhuo Chen, Junjie Yu, Yanjun Li