【XiangShan Biweekly 69】20250203
Happy Chinese New Year! Welcome to XiangShan biweekly column, this is the 69th issue of our biweekly column.
This update mainly includes the latest performance improvements of the Kunminghu architecture.
Biweekly-en
【XiangShan Biweekly 68】20250120
Welcome to XiangShan biweekly column, this is the 68th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the backend fixed a boundary condition where rob failed to flush entries during a redirect, and the memory and cache subsystem fixed the bug of MMU stuck when MissQueue is full under high pressure.
【XiangShan Biweekly 67】20250106
Welcome to XiangShan biweekly column, this is the 67th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed an issue where the corrupt bit was not flushed after ICache MSHR flush, the backend fixed incorrect behavior when fusing lui and fld instructions with the zero register as the destination, and the memory and cache subsystem completed the implementation of Svnapot extension (supports address translation for naturally aligned power-of-2 page sizes) and already merged into master. This update also includes the latest performance improvements of the Kunminghu architecture.
【XiangShan Biweekly 66】20241223
Welcome to XiangShan biweekly column, this is the 66th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed an issue with incorrect RAS predictor updates under power down and up reset, the backend fixed errors in calculating the trap PC for certain interrupts processed in VS mode, and the memory and cache subsystem fixed several bugs releated to misaligned load / store requests. This update also includes the latest performance improvements of the Kunminghu architecture.
【XiangShan Biweekly 65】20241209
Welcome to XiangShan biweekly column, this is the 65th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed incorrect flushing of iTLB in certain situations, the backend fixed calculation errors in scalar/vector half-precision floating-point extensions (Zfh/Zvfh) functional units, and the memory and cache subsystem fixed the bug that a TLB corresponding item is replaced during guest page fault processing. This update also includes the latest performance improvements of the Kunminghu architecture.
【XiangShan Biweekly 64】20241125
Welcome to XiangShan biweekly column, this is the 64th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed BPU s2_fire assignment, the backend completed remaining fields design in dcsr for Debug Module, and the memory and cache subsystem fixed gpaddr generation logic when guest page fault occurs in instruction fetch. This update also includes the latest performance improvements of the Kunminghu architecture.
【XiangShan Biweekly 63】20241111
Welcome to XiangShan biweekly column, this is the 63th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend added reset for FTB pred_data register, the backend merged VS/S/M Mode Double Trap Extension (Ss/mdbltrp) into master, and the memory and cache subsystem fixed the bug in CMO.clean/flush operations when there is an L1 miss and an L2 hit. This update also includes the latest performance improvements of the Kunminghu architecture.
【XiangShan Biweekly 62】20241028
Welcome to XiangShan biweekly column, this is the 62th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed Mux1H on the data path of ECC to Bus Error Unit, the backend is merging VS/S/M Mode Double Trap Extension (Ss/mdbltrp) into master, and the memory and cache subsystem fixed handling logic of vector exceptions. This update also includes the latest performance improvements of the Kunminghu architecture.
【XiangShan Biweekly 61】20241014
Welcome to XiangShan biweekly column, this is the 61th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed a bug in cross-page instruction fetching, the backend Debug extension supported hardware breakpoint debugging for the H extension, and the memory and cache subsystem implemented the vector fault-only-first load instructions. This update also includes the latest performance improvements of the Kunminghu architecture.
【XiangShan Biweekly 60】20240930
Welcome to XiangShan biweekly column, this is the 60th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed the handling of multiple hits in the FTB, the backend supported for virtual interrupt injection, and the memory and cache subsystem added support of vector vstart and trigger. This update also includes the latest performance improvements of the Kunminghu architecture.