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【XiangShan Biweekly 78】20250609

Welcome to XiangShan biweekly column, this is the 78th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the backend has fixed a problem where sstateenx was not correctly generated as a Verilog module, and the memory and cache subsystem have fixed a bug where, on a misaligned and cross-page memory load request that raises an exception, the exception address written into xtval is incorrect. This update also includes the latest performance improvements of the Kunminghu architecture.

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【XiangShan Biweekly 77】20250526

Welcome to XiangShan biweekly column, this is the 77th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed ICache performance counter, the backend fixed functional issues caused by out-of-order reads of xtopi/xtopei registers, and the memory and cache subsystem added handling logic for bus errors on Uncache Store.

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【XiangShan Biweekly 76】20250512

Welcome to XiangShan biweekly column, this is the 76th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the backend has fixed a number of bugs related to interrupt handling, and the memory and cache  have fixed many bugs related to StoreQueue, Uncache, and misalignment. This update also includes the latest performance improvements of the Kunminghu architecture.

  • 分类于 Biweekly-en
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【XiangShan Biweekly 75】20250428

Welcome to XiangShan biweekly column, this is the 75th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend changed FTQ meta SRAM size, the backend fixed an overflow issue of the ROB commit pointer in extreme cases, and the memory and cache subsystem fixed a bug in cbo.zero where RAW violation checks were not performed at cacheline granularity. This update also includes the latest performance improvements of the Kunminghu architecture.

  • 分类于 Biweekly-en
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【XiangShan Biweekly 74】20250414

Welcome to XiangShan biweekly column, this is the 74th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed an issue with SC dual-port SRAM reading and writing to the same address, the backend fixed incorrect selection in vstopi when SEI and LCOFI interrupts are mixed, and the memory and cache subsystem fixed a bug in the custom CSR control logic related to prefetching.

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【XiangShan Biweekly 73】20250331

Welcome to XiangShan biweekly column, this is the 73rd issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed instruction prefetch pipeline handling of high address exceptions, the backend fixed an issue where instruction fusion was not blocked when a trigger fired and an exception occurred, and the memory and cache subsystem fixed several consistency issues in CoupledL2 that violated the CHI protocol. This update also includes the latest performance improvements of the Kunminghu architecture.

  • 分类于 Biweekly-en
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【XiangShan Biweekly 72】20250317

Welcome to XiangShan biweekly column, this is the 72nd issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed bus return corrupt on uncached region handling in IFU, the backend fixed an issue where AMOCAS instructions caused stalls due to incorrect renaming, and the memory and cache subsystem fixed a series of issues related to misaligned load / store violation detection and writeback wakeup logic. This update also includes the latest performance improvements of the Kunminghu architecture.

Additionally, we have also made public the repository for the XiangShan Open Source Processor User Guide: https://github.com/OpenXiangShan/XiangShan-User-Guide and its corresponding webpage: https://docs.xiangshan.cc/projects/user-guide/, as well as the repository for the XiangShan Open Source Processor Design Document: https://github.com/OpenXiangShan/XiangShan-Design-Doc and its corresponding webpage: https://docs.xiangshan.cc/projects/design/. We welcome everyone to read and ask questions.

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【XiangShan Biweekly 71】20250303

Welcome to XiangShan biweekly column, this is the 71st issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend modified RAS overflow behavior to avoid potential deadlocks, the backend enabled out-of-order execution for more CSRR read instructions, and the memory and cache subsystem fixed legacy issues related to exception detection and writeback wakeup on misaligned accesses.

  • 分类于 Biweekly-en
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【XiangShan Biweekly 70】20250217

Welcome to XiangShan biweekly column, this is the 70th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed the Call/Ret condition judgment in RAS during redirection, the backend fixed incorrect fflags generation in unordered vector reduction sum operations, and the memory and cache subsystem fixed multiple bugs related to cbo instructions, including flushing, exception handling, and violation checks. This update also includes the latest performance improvements of the Kunminghu architecture.

  • 分类于 Biweekly-en
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【XiangShan Biweekly 69】20250203

Happy Chinese New Year! Welcome to XiangShan biweekly column, this is the 69th issue of our biweekly column.

This update mainly includes the latest performance improvements of the Kunminghu architecture.