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[XiangShan Biweekly 114] 20261028

Welcome to the XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 114th issue of the biweekly report.

RISC-V Summit China 2026 was successfully held from October 18 to 20 in Shenzhen. Researcher Bao Yungang, Deputy Director of the Institute of Computing Technology, Chinese Academy of Sciences, and Chief Scientist of the Beijing Institute of Open Source Chip, delivered a talk at the summit titled "RISC-V: A 12-Year Journey of Understanding and a 10-Year Outlook on Trends (2015-2035)" (translated from the Chinese title). He reviewed the development of RISC-V, discussed industry trends through 2035, and shared his perspectives on the evolution of open-source chip technology and the industry.

Bao Yungang presenting at the XiangShan Ruyi Ecosystem Conference

During the summit, the XiangShan team hosted the XiangShan Processor Session, featuring presentations on the evolution of XiangShan's high-performance architecture and industrial-grade validation practices. All presentation slides from the session are now publicly available in Talks-and-Publications.

Team photo

Recent XiangShan development includes frontend fixes for address sign extension, ICache ECC checks, and exception propagation; backend support for mnret and dret in the new decoder and an increase in the default ROB capacity to 160 entries; banked CoupledL2 SRAMs and a custom L1–L2 interconnect, alongside fixes for StoreQueue forwarding and fault-address reporting; and an independent asynchronous CUTE clock domain, improved multi-channel memory access scheduling and matrix register writes, and enhanced matrix verification and debugging tools in XSAI. Infrastructure updates strengthen FPGA DiffTest parallel checking and trace recording/replay, improve Kunminghu V2 reference-model integration, fix vector-store exception handling, and optimize store checking.

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[XiangShan Biweekly 113] 20261014

Welcome to the XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 113th issue of the biweekly report.

Regarding the recent development progress of XiangShan, the frontend added VictimBTB to reuse evicted MainBTB entries for branch prediction; the backend implemented a hybrid compressed ROB (CROB), optimized early wakeup and bypass for FMA, and fixed issues in floating-point conversions and instruction legality checks; the memory and cache subsystem added softTLB/softPTW simulation paths supporting two-stage address translation and fixed issues with TLB global attributes and rollback on memory access violations; XSAI integrated a matrix-guided L2 prefetcher and a standalone transpose load engine, while improving matrix debugging and hash comparison; infrastructure updates enhanced FPGA DiffTest, NEMU, Palladium, and AI-assisted debugging tools and fixed GSIM code generation issues; XS-GEM5 advanced model alignment for L2 prefetching and SBuffer behavior, fixed out-of-bounds register access during vector loads, and improved MMIO support, performance regression testing, and build checks.

During RISC-V Summit China 2026, the XiangShan Processor Session will be held on October 18. The session will feature presentations on the evolution of XiangShan's high-performance architecture and industrial-grade validation practices, the application of the UCAgent intelligent agent to XiangShan processors, and a hybrid RISC-V security verification platform for XiangShan processors.

Following the processor session, the XiangShan Developer Conference and XiangShan Ecosystem Conference will both be held on October 20. The XiangShan Developer Conference (09:00–12:30) will focus on technical co-development and sharing, featuring a review of the community’s annual development achievements, recognition of outstanding contributors, an SMT enterprise technology seminar, and the first presentation of the full-stack architectural evolution of the third-generation Kunminghu processor core IP. The XiangShan Ecosystem Conference (13:30–17:30) will focus on collaborative ecosystem building, with presentations on XiangShan and Ruyi technologies, in-depth discussions of foundational RISC-V + AI technologies, AI-themed talks, the launch of an open-source chip community, and a ceremony marking the launch of the Ruyi community co-construction initiative. Ecosystem partners and developers are welcome to follow the event updates and join us in person.

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[XiangShan Biweekly 112] 20260930

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 112th issue of the biweekly report.

Regarding the recent development progress of XiangShan, the frontend fixed issues in CommonHR history and instruction-fetch address checks and optimized uBTB timing; the backend added a unified vector floating-point functional unit and scalar floating-point source operands, while fixing issues related to vector state, CBO, and DiffTest; the memory and cache subsystem integrated ZhuJiang NoC, fixed multiple vector-memory, StoreQueue, exception-handling, and coherence issues, and optimized memory-dependence tracking and timing; XSAI improved matrix debugging support across CUTE, NEMU, and DiffTest; infrastructure updates enhanced FPGA DiffTest, the NEMU reference model, test workloads, sampling and checkpointing, and GSIM; XS-GEM5 continued model alignment and exploration for vector memory access, prefetching, branch prediction, and execution queues.

RISC-V Summit China 2026 will take place from October 18 to 20, 2026, at the Shenzhen Convention and Exhibition Center (Futian). The XiangShan team will present the latest microarchitecture developments and host a XiangShan tutorial at the summit. We look forward to seeing you in Shenzhen!

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[XiangShan Biweekly 111] 20260916

Welcome to the XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 111th issue of the biweekly report.

Regarding the recent development progress of XiangShan, the frontend added BPU S2 override, increased its runahead distance, and fixed an ICache replacement-policy bug; the backend expanded support for vector widening, narrowing, multiply-add, and division, and fixed decoding, bypass, and floating-point bugs; in memory access and caching, F-POP and teacher-student BOP prefetchers were integrated, while LoadQueueReplay gained early wakeup and pipeline optimizations; XSAI added matrix prefetch descriptors to CUTE memory requests, fixed a prefetch livelock, and improved AME DiffTest checks; infrastructure updates improved FPGA DiffTest workflows, optimized the NEMU reference model, expanded test workloads, and fixed GSIM simulation bugs; XS-GEM5 continued aligning Sbuffer, vector writeback, and BPU behavior, and optimized SMT pipeline policies and LSQ contention logic.

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[XiangShan Biweekly 110] 20260902

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 110th issue of the biweekly report.

Regarding the recent development progress of XiangShan, the frontend has fixed several branch-prediction and instruction-fetch issues and optimized uBTB training and IFU/ICache timing; the backend has advanced V3 register-file refactoring; the memory and cache subsystem has fixed several issues while continuing V3 development; XSAI has fixed matrix decoding, memory-access, and operand-wakeup issues and improved DiffTest and CI; in terms of infrastructure, FPGA DiffTest, NEMU/QEMU checkpointing, and GSIM build and simulation capabilities have been enhanced, while XS-GEM5 model calibration and performance exploration have continued.

Special thanks to community contributor muke101 for providing an open-source gem5 implementation of the PHAST memory-dependence prediction algorithm through a GitHub issue. XS-GEM5 further refactored and optimized this implementation.

We are also pleased to announce that the XiangShan team and Professor Trevor E. Carlson of the National University of Singapore will jointly host a workshop entitled Agile Development and Verification for Chips during MICRO 2026 in Greece. Scheduled for October 31, the workshop is now accepting submissions from the community. Please visit the submission website for details and to submit your work. We look forward to meeting you in Greece for an engaging exchange of ideas!

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[XiangShan Biweekly 109] Infrastructure Joins the XiangShan Biweekly!

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 109th issue of the biweekly report.

This issue features a special section on infrastructure, focusing on the agile chip development platform built by the XiangShan team around hardware description languages, functional verification, and performance exploration. Starting with this issue, the biweekly report will also include updates on infrastructure development.

Regarding the recent development progress of XiangShan, the frontend continues to fix bugs and optimize critical-path timing; the backend adds features such as pointer-masking extensions and expands TopDown analysis; the memory and cache subsystem integrates the L2 CDP prefetcher and fixes several bugs; XSAI supports multi-precision transposed loads and improves multi-channel DiffTest and MMA debugging capabilities.

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[XiangShan Biweekly 108] 20260803

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 108th issue of the biweekly report.

On July 21, renowned computer expert Mao Decao visited BOSC and gave a lecture titled "Artificial Intelligence and Processor Chips."

Mao Decao's lecture

Mao's connection with XiangShan goes beyond this visit. He also wrote RISC-V CPU Chip Design: XiangShan Source Code Annotated. He began writing the book in 2021 at the age of 76, working alone for nearly 10 hours a day at times. It took him 3.5 years to complete, by which time he was 79 years old.

The core XiangShan team also had an in-depth discussion with Mao, listening to the valuable experience and profound insights into the industry that he has accumulated over the years. We are deeply honored that Mao agrees with XiangShan's design philosophy. We will continue striving to improve XiangShan and make it a benchmark in the open-source processor field.

Regarding the recent development progress of XiangShan, the frontend continues to optimize timing; the backend fixes some bugs in V2 and calibrates the topdown counter; the memory and cache implement a dual-channel TileLink bus and optimize the LSU; XSAI updates the AME version and fixes several bugs.

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[XiangShan Biweekly 107] 20260720

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 107th issue of the biweekly report.

Regarding the recent development progress of XiangShan, the frontend has fixed timing issues in multiple modules and resolved some bugs reported by the community; the backend has fixed several bugs related to CSR, debug mode, and performance events, and synchronized V2 fixes to V3; in terms of memory access and caching, support for pre-allocated StoreQueue, LoadQueueReplay fast wakeup, and dual-port L1-L2 TileLink bus has been added, along with multiple bug fixes; XSAI has fixed control signals for load/store whole C instructions and added support for configurable multi-channel memory access in CUTE.

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[XiangShan Biweekly 106] 20260706

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 106th issue of the biweekly report.

The XiangShan tutorial at ISCA 2026 was held ~~not so~~ smoothly! Although some students could not present on site due to visa issues, we quickly arranged backup speakers and ultimately ensured that the tutorial was completed with high quality. Special thanks to everyone who follows XiangShan's development!

Regarding the recent development progress of XiangShan, the frontend added support for the 2-fetch feature; the memory subsystem optimized DCache, Sbuffer, and the prefetchers; XSAI supported new matrix memory access modes and updated the instruction extension.

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[XiangShan Biweekly 105] 20260623

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 105th issue of the biweekly report.

The RISC-V Summit Europe has successfully concluded! Professor Bao Yungang, Deputy Director of the Institute of Computing Technology, Chinese Academy of Sciences, and Chief Scientist of the Beijing Open Source Chip Research Institute, shared his experience at the summit and provided insights into the future prospects of RISC-V development. We welcome everyone to engage in discussions with us!

Regarding the recent development progress of XiangShan, the frontend continues to optimize timing; the backend and memory access have fixed some functional bugs while optimizing DCache and Sbuffer performance; XSAI has supported the BF16 extension, and HBL2 has implemented PutFullData for TL-TL and TL-CHI.