跳转至

Publications

XiangShan: An Open-Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards

Published at 2024 IEEE Hot Chips 36 Symposium (HCS). DOI: 10.1109/HCS61935.2024.10665293.

Developing an open-source industrial-grade high-performance processor is a challenging undertaking. With best-in-class performance, XiangShan is an open-source project for RISC-V processors. To maximize overall efficiency, XiangShan adopted a collaborative hardware development model, teaming up with industry partners on processor design, implementation, and verification.

IEEE Micro Special Issue | Hot Chips Slides

Towards Developing High Performance RISC-V Processors Using Agile Methodology

Published at the 55th IEEE/ACM International Symposium on Microarchitecture (MICRO 2022). DOI: 10.1109/MICRO56248.2022.00080.

Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. This paper is awarded all three available badges for artifacts evaluation.

This paper has been selected as an IEEE Micro Top Pick from the 2022 Computer Architecture Conferences. The updated article is published at IEEE Micro's annual special issue in July/August 2023. DOI: 10.1109/MM.2023.3273562.

Paper PDF | IEEE Xplore | BibTeX | Presentation Slides | Presentation Video | IEEE Micro Top Pick

XiangShan Open-Source High Performance RISC-V Processor Design and Implementation

Published at Journal of Computer Research and Development, 2023, 60(3): 476-493 (in Chinese). DOI: 10.7544/issn1000-1239.202221036.

Paper PDF | J-CRAD Online | Presentation Video (in Chinese) | Research Highlight (in Chinese) by Jianlin Gao

Functional Verification for Agile Processor Development: A Case for Workflow Integration

Published as a Cover Article at Journal of Computer Science and Technology, 2023, 38(4): 737−754. DOI: 10.1007/s11390-023-3285-8.

Paper PDF | JCST Website | Presentation Slides | Presentation Video | Perspective by Babak Falsafi

Structured DFT Development Approach for Chisel-Based High Performance RISC-V Processors

Published at 2023 IEEE International Test Conference in Asia (ITC-Asia). DOI: 10.1109/ITC-Asia58802.2023.10301174.

Paper PDF | IEEE Xplore | Presentation Slides

GSIM: Accelerating RTL Simulation for Large-Scale Designs

Published at the 62nd ACM/IEEE Design Automation Conference (DAC 2025). DOI: 10.1109/DAC63849.2025.11133142.

GSIM analyzes the computation overhead of RTL simulation and proposes optimizations at the supernode, node, and bit levels. The resulting simulator successfully runs XiangShan; compared with Verilator, it achieves 7.34× speedup when booting Linux on XiangShan and 19.94× speedup when running CoreMark on Rocket.

Paper PDF | IEEE Xplore

DiffTest-H: Toward Semantic-Aware Communication in Hardware-Accelerated Processor Verification

Published at the 58th IEEE/ACM International Symposium on Microarchitecture (MICRO 2025). DOI: 10.1145/3725843.3756108.

Our paper introduces DiffTest-H, a hardware-accelerated co-simulation framework for processor verification. It covers several optimizations to minimize communication overhead while preserving instruction-level debuggability. This framework is open-sourced and deployed in the XiangShan verification flow, receiving all three available badges for artifact evaluation.

Paper PDF | ACM Digital Library | BibTeX | Presentation Slides

TraceRTL: Agile Performance Evaluation for Microarchitecture Exploration

Published at the 2026 IEEE International Symposium on High Performance Computer Architecture (HPCA 2026). DOI: 10.1109/HPCA68181.2026.11408626.

TraceRTL is an agile, trace-driven methodology that decouples the functional and performance components of CPU RTL designs. It introduces TraceBridge for replaying traces across instruction-set formats and TraceDedup for eliminating redundant traces and accelerating simulation. Evaluated on XiangShan, TraceRTL achieves 99.87% and 99.86% accuracy on SPECint2017 and SPECfp2017, respectively, while TraceDedup accelerates simulation by 1.5×–1.8×.

IEEE Xplore

Democratizing and Accelerating Hardware Verification with Software-Native Optimization

Published at the 2026 ACM/IEEE 53rd Annual International Symposium on Computer Architecture (ISCA 2026). DOI: 10.1109/ISCA66397.2026.00154.

This paper presents UnityChip Verification (UCV), a software-native verification platform that moves event scheduling and control into an explicit software event loop while treating simulators as pluggable backends. Evaluated on XiangShan and RocketChip, UCV delivers up to 25× faster runtime and 76% lower memory usage than Cocotb, and improves throughput by 16.6% when reusing existing verification components.

IEEE Xplore

Research on XiangShan

XiangShan has been used by researchers as the underlying platform for their evaluations. We appreciate their contributions to enhancing XiangShan and strengthening the community.