Publications
Towards Developing High Performance RISC-V Processors Using Agile Methodology
Published at the 55th IEEE/ACM International Symposium on Microarchitecture (MICRO 2022). DOI: 10.1109/MICRO56248.2022.00080.
Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. This paper is awarded all three available badges for artifacts evaluation.
This paper has been selected as an IEEE Micro Top Pick from the 2022 Computer Architecture Conferences. The updated article is published at IEEE Micro's annual special issue in July/August 2023. DOI: 10.1109/MM.2023.3273562.
Paper PDF | IEEE Xplore | BibTeX | Presentation Slides | Presentation Video | IEEE Micro Top Pick
XiangShan Open-Source High Performance RISC-V Processor Design and Implementation
Published at Journal of Computer Research and Development, 2023, 60(3): 476-493 (in Chinese). DOI: 10.7544/issn1000-1239.202221036.
Paper PDF | J-CRAD Online | Presentation Video (in Chinese) | Research Highlight (in Chinese) by Jianlin Gao
Functional Verification for Agile Processor Development: A Case for Workflow Integration
Published as a Cover Article at Journal of Computer Science and Technology, 2023, 38(4): 737−754. DOI: 10.1007/s11390-023-3285-8.
Paper PDF | JCST Website | Presentation Slides | Presentation Video | Perspective by Babak Falsafi
Structured DFT Development Approach for Chisel-Based High Performance RISC-V Processors
Published at 2023 IEEE International Test Conference in Asia (ITC-Asia). DOI: 10.1109/ITC-Asia58802.2023.10301174.
Paper PDF | IEEE Xplore | Presentation Slides
Research on XiangShan
XiangShan has been used by researchers as the underlying platform for their evaluations. We appreciate their contributions to enhancing XiangShan and strengthening the community.
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Imprecise Store Exceptions, EPFL, ISCA'23
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TEESec: Pre-Silicon Vulnerability Discovery for Trusted Execution Environments, OSU & SUSTech, ISCA'23
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Fast, Robust and Transferable Prediction for Hardware Logic Synthesis, Duke, MICRO'23
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Khronos: Fusing Memory Access for Improved Hardware RTL Simulation, PKU, MICRO'23
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A Transfer Learning Framework for High-Accurate Cross-Workload Design Space Exploration of CPU, ICT-CAS, ICCAD'23
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A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT, ICT-CAS, ATS'23
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REMU: Enabling Cost-Effective Checkpointing and Deterministic Replay in FPGA-based Emulation, ICT-CAS, ICCD'23
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Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access, ICT-CAS, TACO