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[XiangShan Biweekly 107] 20260720

Welcome to XiangShan biweekly column! Through this column, we will regularly share the latest development progress of XiangShan. This is the 107th issue of the biweekly report.

Regarding the recent development progress of XiangShan, the frontend has fixed timing issues in multiple modules and resolved some bugs reported by the community; the backend has fixed several bugs related to CSR, debug mode, and performance events, and synchronized V2 fixes to V3; in terms of memory access and caching, support for pre-allocated StoreQueue, LoadQueueReplay fast wakeup, and dual-port L1-L2 TileLink bus has been added, along with multiple bug fixes; XSAI has fixed control signals for load/store whole C instructions and added support for configurable multi-channel memory access in CUTE.

Recent Developments

Frontend

  • Bug fixes
  • Fix the issue where the ITTAGE predictor used the alternative prediction target when the alternative prediction was invalid, leading to incorrect counter updates (#6167)
  • Fix the issue where FTQ did not correctly handle backendExceptionPtr when cleaning up V2 legacy code, causing exceptions to not be reported correctly when jumping to virtual addresses that violate the Sv39/48 specification (#6235)
  • Fix the issue where IFU incorrectly calculated the offset and redirect target when handling a single RVI instruction crossing a page boundary in an MMIO region, leading to incorrect xtval/xepc values and fetching skipping part of the instruction data (#6213)
  • PPA optimizations
  • Decouple the FTQ resolveQueue enqueue logic from the redirect flush logic to avoid an overly long timing path caused by chaining the two (#6239)
  • Remove the ICache wayLookup bypass logic to avoid the SRAM2SRAM timing path from metaArray to dataArray (#6044)
  • Postpone the ICache parity check logic to avoid an overly long timing path caused by performing the check immediately after the dataArray SRAM output (#5733)
  • Debugging tools
  • Add several rolling counters to analyze how performance metrics change over time (#6193)

Backend

  • Bug fixes
  • (V2) Fix the reset values of mstatus.MDT and mnstatus.NMIE, the behavior of writes of 0 to mnstatus.NMIE, and the m/siprios mask logic (#6100)
  • (V3) Sync the fixes related to mstatus.MDT and mnstatus.NMIE (#6223)
  • (V2) Fix CSR behavior for RISC-V Debug Spec 1.0, including the trigger version, dcsr.NMIP updates, and dcsr.CAUSE priority (#6104)
  • (V2) Fix the VSEI priority-index mapping in vstopi (#6131)
  • Debugging tools
  • (V2) Add cpu_cycle and ref_cpu_cycle performance events, and add async bridging for the system-counter path (#6180)
  • (V2) Fix the accounting condition for the frontend_stall_cycle performance event and add backend_stall_cycle accounting (#6121)
  • Code synchronization
  • (V3) Cherry-pick recent V2 backend fixes to V3, including CSR, interrupt, PMP/PMA, debug-mode, and performance-event fixes (#6243)

MemBlock and Cache

  • RTL features
  • Add support for pre-allocated StoreQueue entries (#5834)
  • Add fast wakeup support in LoadQueueReplay for C_MA and C_FF (#6092)
  • Change the L1-L2 TileLink bus to dual-port to reduce blocking between the two cache levels (XSCache #16)
  • Bug fixes
  • Fix incorrect s3 hit-metadata updates when LoadPipe is killed in s2 (#6185)
  • Fix the empty-check logic for Sbuffer CMO drain (#6183)
  • Fix the nMaxPrefetchEntry logic in MissQueue (#6197)
  • Fix cbo.zero writes to Sbuffer (#6228)
  • Remove an incorrect XSError from MissQueue (#6241)

XSAI

  • Bug fixes
  • Fix the control signals for load/store whole C instructions (XSAI #86)
  • RTL features
  • Support configurable multi-channel memory access in CUTE (XSAI #83)
  • Replace coupledL2/huancun/openLLC with the XSAICache repository for the cache system (XSAI #85)
  • Code quality
  • Add switches to control recently added debug output in CUTE (CUTE #24, CUTE #27)
  • Debugging tools
  • Analyze the lifecycle of a uop using traces (XSAI #84)

Performance Evaluation

Processor and SoC parameters are as follows:

Parameters Options
Commit 538ef487c
Date 2026/07/16
L1 ICache 64KB
L1 DCache 64KB
L2 Cache 2MB
L3 Cache 16MB
LSU 3ld2st
Bus protocol CHI
Memory configuration DDR4-3200

The SPEC CPU2006 scores are as follows:

SPECint 2006 @ 3GHz GCC15 XSCC SPECfp 2006 @ 3GHz GCC15 XSCC
400.perlbench 51.60 50.69 410.bwaves 117.89 105.06
401.bzip2 29.70 30.32 416.gamess 58.32 55.79
403.gcc 56.22 40.24 433.milc 70.45 68.03
429.mcf 69.66 62.60 434.zeusmp 77.94 68.08
445.gobmk 39.88 40.41 435.gromacs 38.26 35.16
456.hmmer 55.26 66.99 436.cactusADM 80.28 92.71
458.sjeng 39.49 40.79 437.leslie3d 60.26 60.56
462.libquantum 138.31 308.74 444.namd 42.98 45.22
464.h264ref 69.77 75.31 447.dealII 73.92 73.54
471.omnetpp 43.46 42.85 450.soplex 59.74 70.99
473.astar 32.60 32.11 453.povray 76.38 70.16
483.xalancbmk 83.46 93.14 454.Calculix 42.71 40.68
GEOMEAN 53.86 57.38 459.GemsFDTD 74.24 78.50
465.tonto 54.03 37.61
470.lbm 128.16 146.27
481.wrf 62.22 44.89
482.sphinx3 60.91 63.62
GEOMEAN 65.94 63.51

Compilation parameters are as follows:

Parameters GCC15 XSCC
Compiler gcc15 xscc
Optimization level O3 O3
Memory library jemalloc jemalloc
-march RV64GCB RV64GCB
-ffp-contraction fast fast
Linker optimization -flto -flto
Floating-point optimization -ffast-math -ffast-math
-mcpu - xiangshan-kunminghu

Note: We use SimPoint to sample the programs and create checkpoint images based on our custom checkpoint format, with a SimPoint clustering coverage of 100%. The above scores are estimates based on program segments, not full SPEC CPU2006 evaluations, and may differ from actual chip performance.

Editors: Zhihao Xu, Junxiong Ji, Zhuo Chen, Jiru Sun, Yanjun Li