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【XiangShan Biweekly 63】20241111

Welcome to XiangShan biweekly column, this is the 63th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend added reset for FTB pred_data register, the backend merged VS/S/M Mode Double Trap Extension (Ss/mdbltrp) into master, and the memory and cache subsystem fixed the bug in CMO.clean/flush operations when there is an L1 miss and an L2 hit. This update also includes the latest performance improvements of the Kunminghu architecture.

  • 分类于 Biweekly-en
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【XiangShan Biweekly 62】20241028

Welcome to XiangShan biweekly column, this is the 62th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed Mux1H on the data path of ECC to Bus Error Unit, the backend is merging VS/S/M Mode Double Trap Extension (Ss/mdbltrp) into master, and the memory and cache subsystem fixed handling logic of vector exceptions. This update also includes the latest performance improvements of the Kunminghu architecture.

  • 分类于 Biweekly-en
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【XiangShan Biweekly 61】20241014

Welcome to XiangShan biweekly column, this is the 61th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed a bug in cross-page instruction fetching, the backend Debug extension supported hardware breakpoint debugging for the H extension, and the memory and cache subsystem implemented the vector fault-only-first load instructions. This update also includes the latest performance improvements of the Kunminghu architecture.

  • 分类于 Biweekly-en
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【XiangShan Biweekly 60】20240930

Welcome to XiangShan biweekly column, this is the 60th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed the handling of multiple hits in the FTB, the backend supported for virtual interrupt injection, and the memory and cache subsystem added support of vector vstart and trigger. This update also includes the latest performance improvements of the Kunminghu architecture.

  • 分类于 Biweekly-en
  • 需要 4 分钟阅读时间

【XiangShan Biweekly 59】20240916

Welcome to XiangShan biweekly column, this is the 59th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed a deadlock bug caused by speculative stack in RAS, the backend supported the Resumable Non-Maskable Interrupt (Smrnmi) extension, and the memory and cache subsystem completed CHI2AXI bridge design (OpenNCB). This update also includes the latest performance improvements of the Kunminghu architecture.

  • 分类于 Biweekly-en
  • 需要 4 分钟阅读时间

【XiangShan Biweekly 58】20240902

Welcome to XiangShan biweekly column, this is the 58th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed a design flaw related to software prefetching transitions in the prefetchPipe s1 level state machine, the backend support for the Sstval/Shvstval extensions, and the memory and cache section implemented the 48-bit virtual memory management (Sv48) extension. This update also includes the latest performance improvements of the Kunminghu architecture.

  • 分类于 Biweekly-en
  • 需要 5 分钟阅读时间

【XiangShan Biweekly 57】20240819

Welcome to XiangShan biweekly column, this is the 57th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.

Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed the cross-page exception bug introduced by the IFU refactoring, the backend completed the design of the register file cache, and the memory and cache section completed the CHI-L3 code design and integrated it into the Xiangshan system testing. This update also includes the latest performance improvements of the Kunminghu architecture.