Welcome to XiangShan biweekly column, this is the 64th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed BPU s2_fire assignment, the backend completed remaining fields design in dcsr for Debug Module, and the memory and cache subsystem fixed gpaddr generation logic when guest page fault occurs in instruction fetch. This update also includes the latest performance improvements of the Kunminghu architecture.
Welcome to XiangShan biweekly column, this is the 63th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend added reset for FTB pred_data register, the backend merged VS/S/M Mode Double Trap Extension (Ss/mdbltrp) into master, and the memory and cache subsystem fixed the bug in CMO.clean/flush operations when there is an L1 miss and an L2 hit. This update also includes the latest performance improvements of the Kunminghu architecture.
Welcome to XiangShan biweekly column, this is the 62th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed Mux1H on the data path of ECC to Bus Error Unit, the backend is merging VS/S/M Mode Double Trap Extension (Ss/mdbltrp) into master, and the memory and cache subsystem fixed handling logic of vector exceptions. This update also includes the latest performance improvements of the Kunminghu architecture.
Welcome to XiangShan biweekly column, this is the 61th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed a bug in cross-page instruction fetching, the backend Debug extension supported hardware breakpoint debugging for the H extension, and the memory and cache subsystem implemented the vector fault-only-first load instructions. This update also includes the latest performance improvements of the Kunminghu architecture.
Welcome to XiangShan biweekly column, this is the 60th issue of our biweekly column. Through this column, we will regularly introduce the progress of XiangShan, hoping to learn and improve together with you.
Recently, various teams working on Kunminghu have continued to advance optimizations in area, timing, and power consumption. In addition, the frontend fixed the handling of multiple hits in the FTB, the backend supported for virtual interrupt injection, and the memory and cache subsystem added support of vector vstart and trigger. This update also includes the latest performance improvements of the Kunminghu architecture.