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XiangShan Design Document

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XiangShan-Design-Doc

XiangShan Design Document

XiangShan-Design-Doc

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Frontend
Frontend
- Branch Prediction Unit
  Branch Prediction Unit
- Fetch Target Queue
  Fetch Target Queue
- Instruction Fetch Unit
  Instruction Fetch Unit
  - Pre-Decoder
- Instruction Cache
  Instruction Cache
  - MainPipe
  - PrefetchPipe
  - WayLookup
  - Array
  - MissUnit
  - Replacer
  - CtrlUnit
- PC Class
  PC Class
Backend
Backend
- Control Block (CtrlBlock)
  Control Block (CtrlBlock)
  - Decode
  - Rename
  - Dispatch
  - Reorder Buffer
- Data Path (DataPath)
  Data Path (DataPath)
- Scheduling and Issue
  Scheduling and Issue
- Execution
  Execution
  - ExuBlock
  - ExuUnit
- Function Unit (FunctionUnit)
  Function Unit (FunctionUnit)
- Vector Floating-Point Unit (VFPU)
- Control and Status Registers (CSR)
- Hardware Performance Monitor (HPM)
- Debug Module
Memory System
Memory System
- Load-Store Unit (LSU)
  Load-Store Unit (LSU)
- Data Cache
  Data Cache
- Memory Management Unit (MMU)
  Memory Management Unit (MMU)
  - L1TLB
  - Repeater
  - L2TLB
    
    L2TLB
    
    Page Cache
    
    Page Table Walker
    
    Last Level Page Table Walker
    
    Hypervisor Page Table Walker
    
    Miss Queue
    
    Prefetcher
  - PMP & PMA
Cache Subsystem
Cache Subsystem
- L2 Cache
  L2 Cache
  - L2 Cache (CoupledL2)
  - Channel A Request Buffer (RequestBuffer)
  - Request Arbiter and Main Pipeline
  - Directory (Directory)
  - Data SRAM (DataStorage)
  - MSHR
  - Upstream TileLink Channels
    Upstream TileLink Channels
    
    SinkA
    
    SinkC
    
    GrantBuffer
  - Downstream CHI Channels
    Downstream CHI Channels
    
    TXREQ
    
    RXRSP
    
    RXDAT
    
    RXSNP
    
    TXDAT
    
    TXRSP
    
    P-Credit Management
    
    Link Layer Controller (LinkMonitor)
  - MMIO Bridge (MMIOBridge)
  - Error Handling

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